1. Field of the Invention
This invention relates to a high voltage level shifter circuit comprised of CMOS transistor devices.
2. Statement of the Prior Art
Conventional CMOS voltage level shifter circuits are relatively unreliable for high voltage applications. As a result of the prior art level shifter circuit implementation and deficiencies in device processing, the diode junction of certain CMOS transistor devices (e.g. n-channel FETs) become back biased so as to consequently cause transistor breakdown and failure when relatively low input voltages, typically in the order of 15 volts, are exceeded. Hence, due to the high susceptibility for breakdown of the component transistor devices, the output voltage swing of the prior art level shifter circuits is undesirably limited.
Examples of conventional voltage level shifter circuits are disclosed in the following U.S. Patents:
U.s. pat No. 3,942,043--Mar. 2, 1976 PA1 U.s. pat. No. 4,039,862--Aug. 2, 1977
However, none of the prior art level shifter patents shows a circuit comprising first and second p-channel field effect transistors interconnected with first and second pairs of series connected n-channel field effect transistors, as disclosed and claimed in the instant patent application, to prevent low voltage transistor breakdown and to thereby extend the range of the level shifter output voltage swing.